Chisel Shiftregister示例

Question

我对scala和Chisel很新.我试图创建一个动态大小的Shiftregister示例,但我不确定以下代码是否正确.如果有人可以审查它会很好:

import Chisel._

class Shiftregister(length: Int) extends Module {
    val io = new Bundle {
        val clk        = UInt(INPUT,  1)
        val load       = UInt(INPUT,  1) // 1 read from s_data_in, 0 read from p_data_in
        val s_data_in  = UInt(INPUT,  1)
        val s_data_out = UInt(OUTPUT, 1)
        val p_data_in  = UInt(INPUT,  length)
        val p_data_out = UInt(OUTPUT, length)
    }

    val bitfield = Reg(init = UInt(length))

    when (io.load.toBool()) {
        bitfield := Cat(io.s_data_in, bitfield(length, 1))
    }
    .otherwise {
        bitfield := io.p_data_in
    }
    io.p_data_out := Reg(next = bitfield)
    io.s_data_out := Reg(next = bitfield(0))
}

class ShiftregisterTest(c: Shiftregister) extends Tester(c, Array(c.io)) {
    defTests {
        true
    }
}

object Shiftregister {
    def main(args: Array[String]): Unit = {
        chiselMainTest(Array[String]("--backend", "c", "--genHarness", "--v"), () => Module(new Shiftregister(16))){c => new ShiftregisterTest(c)}
    }
}

我试图创建以下VHDL代码的等价物:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY shiftregister IS
    GENERIC(
        length: positive
    );
    PORT(
        clk: IN STD_LOGIC;
        load: IN STD_LOGIC; -- 1 read from s_data_in, 0 read from p_data_in
        s_data_in: IN STD_LOGIC := '0';
        s_data_out: OUT STD_LOGIC;
        p_data_in: IN STD_LOGIC_VECTOR(length-1 DOWNTO 0) := (others => '0');
        p_data_out: OUT STD_LOGIC_VECTOR(length-1 DOWNTO 0)
    );
END ENTITY shiftregister;

ARCHITECTURE synthesis OF shiftregister IS
    SIGNAL bitfield: STD_LOGIC_VECTOR(length-1 DOWNTO 0);
BEGIN
    PROCESS (clk) IS
    BEGIN
        IF RISING_EDGE(clk) THEN
            IF load = '0' THEN
                bitfield <= p_data_in;
            ELSE
                bitfield(length-1 DOWNTO 0) <= s_data_in & bitfield(length-1 DOWNTO 1);
            END IF;
        END IF;
    END PROCESS;
    p_data_out <= bitfield;
    s_data_out <= bitfield(0);
END ARCHITECTURE synthesis;

Answer 1

以下是我的评论:

首先,"clk"是不必要的,因为时钟隐含在Chisel中.

其次,对于某些信号,您可能应该使用Bool()而不是UInt(width = 1).

val load = Bool(INPUT)

虽然这无疑是一种风格意见,但它可以防止以后需要做.toBool演员.

第三,这条线不符合你的意图:

val bitfield = Reg(init = UInt(length))

那就是创建一个寄存器,在重置时初始化为值"length"的UInt().相反,要创建宽度为"length"的寄存器,请执行以下操作:

val bitfield = Reg(outType=UInt(width=length))

你也可以使用

val bitfield = Reg(UInt(width=length))

由于Reg()的默认参数是您要创建的寄存器的"类型".但是,IMO,可能有点含糊不清.如果要将寄存器初始化为0,请执行以下操作:

val bitfield = Reg(init = UInt(0, length))