VHDL 2D整数数组

Question

任何人都可以告诉我为什么这个代码无法模拟.行为检查语法是正确的.我正在尝试创建一个整数的2D数组,这是不变的.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.STD_LOGIC_ARITH.all;

--selection function 1

entity S1 is
    Port ( 
    i : in  STD_LOGIC_VECTOR (5 downto 0);
    o : out  STD_LOGIC_VECTOR (3 downto 0));
end S1;

architecture Behavioral of S1 is

  type matrix is array(0 downto 3, 0 downto 15) of INTEGER range 0 to 15;
  constant m : matrix := 
      ((14, 4, 13, 1, 2, 15, 11, 8, 3, 10, 6, 12, 5, 9, 0, 7),
      (0, 15, 7, 4, 14, 2, 13, 1, 10, 6, 12, 11, 9, 5, 3, 8),
      (4, 1, 14, 8, 13, 6, 2, 11, 15, 12, 9, 7, 3, 10, 5, 0),
      (15, 12, 8, 2, 4, 9, 1, 7, 5, 11, 3, 14, 10, 0, 6, 13));

  signal row : STD_LOGIC_VECTOR(1 downto 0);
  signal col : STD_LOGIC_VECTOR(3 downto 0);

begin

    row <= i(5) & i(0);
    col <= i(4 downto 1);
    o <= conv_std_logic_vector(m(conv_integer(row), conv_integer(col)), 4);

end Behavioral;

解:它应该是(0到N)而不是(0到N).错误消息不是那么清楚.

Answer 1

您需要一个更好的语法检查器.

GHDL报告:

ghdl -a --ieee=synopsys nullrange.vhd
nullrange.vhd:18:7: too many elements associated
nullrange.vhd:18:7: range length is beyond subtype length
nullrange.vhd:18:7: too many elements associated
nullrange.vhd:18:7: range length is beyond subtype length
nullrange.vhd:19:6: too many elements associated
nullrange.vhd:19:6: subaggregate length mismatch
nullrange.vhd:20:6: too many elements associated
nullrange.vhd:20:6: subaggregate length mismatch
nullrange.vhd:21:6: too many elements associated
nullrange.vhd:21:6: subaggregate length mismatch
nullrange.vhd:17:10: default value length does not match object type length
ghdl: compilation error

(0 downto 3)被称为"零范围",这是合法的,但没有成员.所以初始化聚合中有太多元素......