两个补码VHDL

Question

我只是想在VHDL中创建一个简单的二进制补码设备,但它正在抛弃这个非常烦人的错误,而且我不确定我做错了什么.可能是非常愚蠢的......错误是"错误(10327):twocompliment.vhd(21)的VHDL错误:无法确定运算符的定义""nand"" - 找到0个可能的定义"

代码是

library ieee;
use ieee.std_logic_1164.all; 
use ieee.numeric_std.all;
entity twoscompliment is
      generic
      (
              Nbits : positive := 8 
       );
 port 
( 
           --Inputs
           A : in std_logic_vector (Nbits-1 downto 0);
           --Outputs
           Y : out std_logic_vector (Nbits downto 0)
);
end twoscompliment;

architecture twoscompliment_v1 of twoscompliment is
 begin
  Y <= std_logic_vector(unsigned(A NAND '1') + '1');
 end twoscompliment_v1;

任何帮助都是极好的!

Answer 1

在我看来,你试图否定输入数字...也许我错过了一些重要的东西,但其他答案提供了一个解决方案,在实现目标的同时,似乎比他们需要的更加混淆了一步.

除了丑陋的转变,出了什么问题

y <= std_logic_vector(-signed(resize(unsigned(A)), y'length));

当然,我认为如果A和Y应该代表有符号数字(或无符号数字),它们应该表示为:

library ieee;
use ieee.numeric_std.all;
entity twoscomplement is
  generic
  (
     Nbits : positive := 8 
  );
  port 
  ( 
     A : in  unsigned (Nbits-1 downto 0);
     Y : out signed   (Nbits downto 0)
  );
end entity twoscomplement;

architecture a1 of twoscomplement is
begin
  Y <= -signed(resize(A, Y'length));
end architecture;

我们来看看结果:

entity test_twoscomplement is
end entity;

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture test of test_twoscomplement is
    signal A : unsigned (7 downto 0);
    signal Y : signed(8 downto 0);
begin
    dut : entity work.twoscomplement port map (A => A, Y=>Y); 

    process
    begin
       for i in 0 to 255 loop
         A <= to_unsigned(i, A'length);
         wait for 1 ns;
         assert to_integer(Y) = -i severity error;
       end loop;
       report "tests done";
       wait;
     end process;
end architecture;

使用GHDL运行:

$ ghdl -a twoscomp.vhd 
$ ghdl --elab-run test_twoscomplement
twoscomp.vhd:40:8:@256ns:(report note): tests done

成功!