同时使用case语句和if-else？

Question

我是硬件初学者.

在学习Verilog HDL时,由于缺乏系统学习,我在学习期间很容易迷路.

我正在尝试编写下面状态图中指定的机器的Verilog HDL行为描述.

我在case语句中使用if-else语句,这给了我关于这些行的语法错误.

与Java或C++不同,Verilog几乎没有关于错误的来源.

你知道问题是什么吗？

我的代码附在下面:

module foo(y_out, state, x_in, clk, reset);

    input x_in, clk, reset;
    output reg y_out;
    parameter s0 = 3'b000, s1 = 3'b001, s2 = 3'b010, s3 = 3'b011, s4 = 3'b100;
    output reg[2:0] state;
    reg[2:0] next_state;

    always @(posedge clk) begin
        if(reset == 1'b0) state <= s0;
        else state <= next_state;
    end
    always @(state, x_in) begin
        y_out = 0;
        next_state = s0;
        case(state, x_in)
        s0:
            if (!x_in) begin
                next_state = s3;
                y_out = 1'b0;
            end
            else begin
                next_state = s4;
                y_out =1'b1;
            end
        s1:
            if (!x_in) begin
                next_state = s1;
                y_out = 1'b0;
            end
            else begin
                next_state = s4;
                y_out =1'b1;
            end
        s2: if (!x_in) begin
                next_state = s2;
                y_out = 1'b0;
            end
            else begin
                next_state = s0;
                y_out =1'b1;
            end
        s3: if (!x_in) begin
                next_state = s1;
                y_out = 1'b0;
            end
            else begin
                next_state = s2;
                y_out =1'b1;
            end
        s4: if (!x_in) begin
                next_state = s2;
                y_out = 1'b0;
            end
            else begin
                next_state = s3;
                y_out =1'b0;
            end
        default begin
            next_state = s0;
            y_out = 1'b0;
        end
        endcase
    end
endmodule

module t_foo;

    wire t_y_out, t_state;
    reg t_x_in, t_clock, t_reset;

    foo M1(t_y_out, t_state, t_x_in, t_clock, t_reset);

    initial #200 $finish;
    initial begin
        t_reset = 0;
        t_clock = 0;
        #5 t_reset = 1;
      repeat (16)
        #5 t_clock = ~t_clock;
    end

    initial begin
        t_x_in = 0;
        #15 t_x_in = 1;
      repeat (8)
        #10 t_x_in = ~t_x_in;
    end
    initial begin
       $monitor("ABC: %d, x_in: %d, Clock: %d, Reset: %d", state, t_x_in, t_clock, t_reset);
       $dumpfile("5_41_wv.vcd");
       $dumpvars;
    end
endmodule

Answer 1

case语句期望单个项目,如果这是基于多个wire/regs,那么它们需要使用连接{}.

我会避免使用类似的东西always @(state, x_in) begin,只是写always @* begin.@*将处理敏感度列表.

使用连接运算符将允许您删除if语句:

 always @* begin
   y_out = 0;
   next_state = s0;
   case({state, x_in}) //Added {}
    {s0, 1'b0}: 
      begin
        next_state = s3;
        y_out      = 1'b0;
      end
    {s0, 1'b1}:
      begin 
        next_state = s4;
        y_out      = 1'b1;
      end
    {s1, 1'b0}: 
      begin
        next_state = s1;
        y_out      = 1'b0;
      end
    {s1, 1'b1}:
      begin
        next_state = s4;
        y_out      = 1'b1;
      end

使用a casez将允许您添加不关心next_state逻辑:

 always @* begin
   y_out = 0;
   next_state = s0;
   casez({state, x_in}) //Added {}
    {s0, 1'bx}: //Do not care about the state of x_in
      begin
        next_state = s3;
        y_out      = 1'b0;
      end
    {s1, 1'b0}: 
      begin
        next_state = s1;
        y_out      = 1'b0;
      end
    {s1, 1'b1}:
      begin
        next_state = s4;
        y_out      = 1'b1;
      end