在VHDL中声明实体内的数组

Question

我正在尝试建立一个缓冲区,以便为小型CPU设计保存16位,16位宽的指令.

我需要一种从我的测试平台将指令加载到缓冲区的方法.所以我想使用一个std_logic_vectors数组来实现这一目标.但是,我收到语法错误,我不知道为什么(或者如果我允许在VHDL中执行此操作).

语法错误位于我声明的行 instructions

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;




entity instruction_buffer is
    port
    (
    reset               : in std_logic;
    instructions        : in array(0 to 15) of std_logic_vector(15 downto 0);
    instruction_address : in  std_logic_vector(3 downto  0);
    clk                 : in std_logic;
    instruction_out     : out std_logic_vector(15 downto 0)
    );
end instruction_buffer;

我也试过这样做,但后来我的实体端口映射中出现语法错误,告诉我这std_logic_vector是一个未知的类型.我发誓,VHDL的语法错误没有C哈哈那么有意义

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

package instructionBuffer is
    type instructionBuffer is array(0 to 15) of std_logic_vector (15 downto 0);
end package instructionBuffer;

entity instruction_buffer is
    port
    (
    instruction_address : in  std_logic_vector(3 downto  0);
    clk                 : in std_logic;
    instruction_out     : out std_logic_vector(15 downto 0)
    );
end instruction_buffer;

Answer 1

无需拆分成两个文件,只需将所有代码放入一个文件即可.您还可以在包中使用泛型来实现可伸缩性:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

package instruction_buffer_type is
constant INSTRUCTION_BUFFER_ADDRESS : integer := 4;  --bits wide
constant INSTRUCTION_BUFFER_DATA    : integer := 16; --bits wide
type instructionBuffer is array(0 to 2**INSTRUCTION_BUFFER_ADDRESS -1) of std_logic_vector (INSTRUCTION_BUFFER_DATA -1 downto 0);
end package instruction_buffer_type;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

use work.instruction_buffer_type.all;

entity instruction_buffer is
    port
    (
    instruction_address : in  std_logic_vector(INSTRUCTION_BUFFER_ADDRESS-1 downto  0);
    instructions        : in instructionBuffer;
    clk                 : in std_logic;
    instruction_out     : out std_logic_vector(INSTRUCTION_BUFFER_DATA-1 downto 0)
    );
end instruction_buffer;

Answer 2

我搞定了:

在一个文件中,我有以下内容:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

package instruction_buffer_type is
    type instructionBuffer is array(0 to 15) of std_logic_vector (15 downto 0);
end package instruction_buffer_type;

然后在另一个我有:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

use work.instruction_buffer_type.all;

entity instruction_buffer is
    port
    (
    instruction_address : in  std_logic_vector(3 downto  0);
    instructions        : in instructionBuffer;
    clk                 : in std_logic;
    instruction_out     : out std_logic_vector(15 downto 0)
    );
end instruction_buffer;

很明显,这种语言是一个政府项目.这太过分了.