用VHDL编写寄存器文件

Question

我正在尝试用VHDL编写寄存器文件.该文件包含16个64位寄存器.每个周期读取两个寄存器并写入一个寄存器(假设写入已启用).应该有一个数据旁路(转发),这样如果我们在一个周期内读取和写入同一个寄存器,那么刚写入的值就会直接转发到输出.

我的想法是在上升沿写入并在时钟的下降沿读取,以便在一个周期内完成此操作.但是,我的设计不起作用(不是我预期的,因为我不相信在检查上升沿的if块中检查下降沿将按预期工作).

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity register_file is   
    port
    (
    outA          : out std_logic_vector(63 downto 0);
    outB          : out std_logic_vector(63 downto 0);
    input         : in  std_logic_vector(63 downto 0);
    writeEnable   : in std_logic;
    regASel       : in std_logic_vector(5 downto 0);
    regBSel       : in std_logic_vector(5 downto 0);
    writeRegSel   : in std_logic_vector(5 downto 0);
    clk           : in std_logic
    );
end register_file;

architecture behavioral of register_file is
type registerFile is array(0 to 15) of std_logic_vector(63 downto 0);
signal registers : registerFile;
begin

    regFile: process(clk)
    begin
        if rising_edge(clk) then 
            if(writeEnable = '1') then
                registers(to_integer(unsigned(writeRegSel))) <= input;
            end if;
            if falling_edge(clk) then
                outA <= registers(to_integer(unsigned(regASel)));
                outB <= registers(to_integer(unsigned(regBSel)));
            end if;
        end if;
        if falling_edge(clk) then
                outA <= registers(to_integer(unsigned(regASel)));
                outB <= registers(to_integer(unsigned(regBSel)));
        end if;
    end process;
end behavioral;

任何帮助,将不胜感激.

Answer 1

提交的VHDL代码具有以下构造:

...
if rising_edge(clk) then
  ...
  if falling_edge(clk) then
  ...

这将使死代码,因为两者rising_edge并falling_edge在同一时间不可能是真实的.此外,使用上升沿和下降沿的想法通常会导致设计和综合问题.

为了获得最佳时序,易于设计和合成约束,我建议仅使用上升沿,除非必须同时使用上升沿和下降沿.

通过在同一周期中绕过读取A和B的写入数据,寄存器文件可能如下所示:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity register_file is
  port(
    outA        : out std_logic_vector(63 downto 0);
    outB        : out std_logic_vector(63 downto 0);
    input       : in  std_logic_vector(63 downto 0);
    writeEnable : in  std_logic;
    regASel     : in  std_logic_vector(3 downto 0);
    regBSel     : in  std_logic_vector(3 downto 0);
    writeRegSel : in  std_logic_vector(3 downto 0);
    clk         : in  std_logic
    );
end register_file;


architecture behavioral of register_file is
  type registerFile is array(0 to 15) of std_logic_vector(63 downto 0);
  signal registers : registerFile;
begin
  regFile : process (clk) is
  begin
    if rising_edge(clk) then
      -- Read A and B before bypass
      outA <= registers(to_integer(unsigned(regASel)));
      outB <= registers(to_integer(unsigned(regBSel)));
      -- Write and bypass
      if writeEnable = '1' then
        registers(to_integer(unsigned(writeRegSel))) <= input;  -- Write
        if regASel = writeRegSel then  -- Bypass for read A
          outA <= input;
        end if;
        if regBSel = writeRegSel then  -- Bypass for read B
          outB <= input;
        end if;
      end if;
    end if;
  end process;
end behavioral;

请注意,*Sel中的"地址"仅减少到4位,以匹配寄存器文件中的16个必需条目,正如Daniel Kamil Kozar所指出的那样.

模拟中没有检查X值,但Is_X如果需要,可以添加 功能.