在verilog中实现PIPO

Question

我期待在verilog HDL中实现32位并行并行输出.这是我写的代码......

module pipo(input_seq, answer,reset, clock);
   input [31:0] input_seq;
   input        reset,clock;
   output [31:0] answer;

   always @ (reset)
     begin
        if(!reset)
          begin
             answer[31:0]<=1'b0;
          end
     end

   always @ (posedge clock)
     begin
        answer[31:1]<=input_seq[30:0];  
     end

endmodule

但是,这会导致以下错误日志(使用iverilog):

pipo.v:10: error: answer['sd31:'sd0] is not a valid l-value in pipo.
pipo.v:4:      : answer['sd31:'sd0] is declared here as wire.
pipo.v:16: error: answer['sd31:'sd1] is not a valid l-value in pipo.
pipo.v:4:      : answer['sd31:'sd1] is declared here as wire.
Elaboration failed

有什么问题？

Answer 1

您正在使用answer寄存器,但它被声明为电线.Wire是连接两个点的东西,因此没有任何驱动力.另一方面reg可以存储价值和驱动力.

变更申报answer到reg它应该帮助.

output reg [31:0] answer;