使用泛型参数作为端口数组长度

Question

我想做的事:

entity FIRfilter is
   generic (
      NTAPS : integer );
   port (
      -- ...
      h : in array(0 to NTAPS-1) of std_logic_vector(15 downto 0) );
end FIRfitler;

但是行上的语法h不正确.

这个问题类似: 如何在VHDL中将整数数组指定为泛型？ 但这并没有让我在实例化时获得通用的数量.这甚至可能吗？

Answer 1

如果在包中声明无约束的数组类型,则可以基于泛型约束数组,如下面的代码所示:

library ieee; use ieee.std_logic_1164.all;

package FIRfilter_pkg is
  type x_t is array(natural range <>) of std_logic_vector(15 downto 0);
end package;


library ieee; use ieee.std_logic_1164.all;
library work; use work.FIRfilter_pkg.all;

entity FIRfilter is
   generic (
      NTAPS : integer );
   port (
     x : in x_t(0 to NTAPS-1);
     z : out std_logic_vector(15 downto 0) );  -- For simple example below
end FIRfilter;


library ieee; use ieee.numeric_std.all;

architecture syn of FIRfilter is
begin
  z <= std_logic_vector(unsigned(x(0)) + unsigned(x(1)));  -- Usage example
end architecture;