VHDL等于运算符:std_logic和std_ulogic的不同行为

Question

我有两个设计:

library ieee;
use ieee.std_logic_1164.all;

entity eq_test1 is

  port (a,b : IN std_logic_vector (1 downto 0);
        o   : OUT std_logic); 
end eq_test1;

architecture strange_behavior of eq_test1 is
begin  
    P: process (a,b)
    begin
        if a = b then o <= '1';
        else o <= '0';
        end if;
    end process P;
end strange_behavior;

强制在Modelsim中具有"00"并且b具有"0L"表示o变为"0".因此L不被解释为0,"00"="0L"为假.好.

但是当我采用相同的设计并添加时

use ieee.std_logic_unsigned.all;

到列表中,行为是不同的.然后"00"="0L"返回true,因此L IS与0相同(0变为"1").包含未签名的包,即使"0X"="0Z"也返回true.

有谁能解释为什么？

Answer 1

添加use ieee.std_logic_unsigned.all;就像向Synopsys库打开Pandora的盒子一样.在下面显示的深度潜水之后,结论是在这种情况下std_logic_unsigned包通过表使值"0"和"L"相等.

将"="运算符重新定义为以下内容时,调用将启动:

function "="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
    return   UNSIGNED(L) = UNSIGNED(R);
end;

然而,这仅仅是开始,因为std_logic_unsigned包含 use IEEE.std_logic_arith.all;,它定义了类型:

type UNSIGNED is array (NATURAL range <>) of STD_LOGIC;

因此,"="中UNSIGNED的比较会导致调用std_logic_arith函数:

function "="(L: UNSIGNED; R: UNSIGNED) return BOOLEAN is
    -- synopsys subpgm_id 341
    constant length: INTEGER := max(L'length, R'length);
begin
    return bitwise_eql( STD_ULOGIC_VECTOR( CONV_UNSIGNED(L, length) ),
            STD_ULOGIC_VECTOR( CONV_UNSIGNED(R, length) ) );
end;

在这个函数中,CONV_UNSIGNED很有趣:

function CONV_UNSIGNED(ARG: UNSIGNED; SIZE: INTEGER) return UNSIGNED is
    constant msb: INTEGER := min(ARG'length, SIZE) - 1;
    subtype rtype is UNSIGNED (SIZE-1 downto 0);
    variable new_bounds: UNSIGNED (ARG'length-1 downto 0);
    variable result: rtype;
    -- synopsys built_in SYN_ZERO_EXTEND
    -- synopsys subpgm_id 372
begin
    -- synopsys synthesis_off
    new_bounds := MAKE_BINARY(ARG);
    if (new_bounds(0) = 'X') then
        result := rtype'(others => 'X');
        return result;
    end if;
    result := rtype'(others => '0');
    result(msb downto 0) := new_bounds(msb downto 0);
    return result;
    -- synopsys synthesis_on
end;

现在我们接近了,因为上面的调用:

function MAKE_BINARY(A : UNSIGNED) return UNSIGNED is
    -- synopsys built_in SYN_FEED_THRU
    variable one_bit : STD_ULOGIC;
    variable result : UNSIGNED (A'range);
begin
    -- synopsys synthesis_off
        for i in A'range loop
            if (IS_X(A(i))) then
                assert false
                report "There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)."
                severity warning;
                result := (others => 'X');
                return result;
            end if;
            result(i) := tbl_BINARY(A(i));
        end loop;
        return result;
    -- synopsys synthesis_on
end;

在这里我们有'L'等于'0'的原因,因为tbl_BINARY是一个常量,定义为:

type tbl_type is array (STD_ULOGIC) of STD_ULOGIC;
constant tbl_BINARY : tbl_type :=
    ('X', 'X', '0', '1', 'X', 'X', '0', '1', 'X');

要理解此映射,与STD_ULOGIC中的值定义一致是有用的:

std_ulogic: ( 'U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-');

tbl_BINARY: ( 'X', 'X', '0', '1', 'X', 'X', '0', '1', 'X');

这表明在通过tbl_BINARY转换之后,等效组是('U','X','Z','W',' - '),('0','L')和('1', 'H').

结束评论是即使通过std_logic_unsigned包驻留在名为"ieee"的库中,该包也不是像VHDL那样的IEEE标准,而是Synopsys包.该软件包以及其他相关的Synopsys软件包已经存在了一段时间,并且被广泛使用.

但是,您可以考虑使用IEEE标准包numeric_std.