VHDL - 取决于泛型的条件属性声明

Pas*_*out 3 vhdl

如何编写一个代码段来评估泛型并相应地创建(或不创建)属性?

例子 :

if G_MY_GENERIC then
    attribute my_attribute_typ : string;
    attribute my_attribute_typ of signal_having_an_attr : signal is "value";
else
    --nothing is created
end if;
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Oll*_*ieB 5

完全可以写出类似的东西,但该属性只会在 generate 语句的范围内可见。

g_something: if test_condition generate
   attribute my_attribute_typ : string;
   attribute an_attribute of my_attribute_typ: signal is "value";
begin
    -- attribute is visible in this scope

    p_my_process: process(clk)
    begin
        -- attribute is also visible here
    end process;
end generate;

-- but not here
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