Verilog总是阻止声明

Question

我只是想知道这两个陈述之间的区别

always @(posedge CLK)
    begin
       state <= next_state;
    end

和:

always @(CLK)
    begin
     case(CLK)
        1'b1:
           state <= next_state;
        1'b0:
           state <= state;
    end

两者之间有区别吗？

谢谢

Answer 1

不完全的.posedge检测这些转换(来自LRM):

Table 43—Detecting posedge and negedge
To   0       1       x       z
From
0    No edge posedge posedge posedge
1    negedge No edge negedge negedge
x    negedge posedge No edge No edge
z    negedge posedge No edge No edge

因此,posedge例如,0-> x是a .您的第二个示例仅检测CLK最终为1的情况,因此错过了0-> x和0-> z.