VHDL std_logic_vector索引与"downto"

Question

我想分别设置std_logic_vector的位,以便轻松地为各个位或位组设置注释.这是我有的:

signal DataOut : std_logic_vector(7 downto 0);
...
DataOut <= (                        5=>'1',     -- Instruction defined
                                    4=>'1',     -- Data length control bit, high=8bit bus mode selected
                                    3=>'1',     -- Display Line Number ctrl bit, high & N3 option pin to VDD=3 lines display
                                    2=>'0',     -- Double height font type control byte, not selected
                                    1 downto 0=>"01",   -- Select Instruction table1
                                    others=>'0' -- for bits 6,7
                                    );

但是,我对"downto"语句有疑问,使用Xilinx ISE时出现以下错误:

Type std_ulogic does not match with a string litteral

避免使用等效的任何解决方案

1=>'0',
0=>'1',

并允许我逐块设置？

Answer 1

X downto Y => 'A'当A是数组的元素时,赋值是正确的.例如,此代码段是正确的:

1 downto 0 => '1',

而这个片段是错误的:

1 downto 0 => "01",

因此,您的任务是非法的.作为您的代码,您可以指定为:

DataOut <= (                        5 downto 3 =>'1',     
                                    2 downto 1 =>'0',     
                                    0 => '1',  
                                    others=>'0' 
                                    );

如果要通过数组访问/分配,可以使用连接:

DataOut <= Something_0 & Something_1 & "01";

虽然Something_*是std_logic_vector