VHDL:如何在inout端口上设置一个值？

Question

我正在尝试测试一个VHDL组件,但我似乎无法得到这个inout端口给我任何行为.我已经尝试将端口设置为从"1"到" - "的所有内容,但它仍然在模拟中显示为"U".任何可能错误的消化？

Answer 1

对于Inout端口(例如在RAM中):

....
port(
    data    :inout std_logic_vector (DATA_WIDTH-1 downto 0);
....
-- Memory Write Block
-- Write Operation : When we = 1, cs = 1
  MEM_WRITE: process (address, cs, we, data, address_1, cs_1, we_1, data_1) begin
    if (cs = '1' and we = '1') then
       mem(conv_integer(address)) <= data;
    end if;
  end process;

 -- Tri-State Buffer control
  data <= data_out when (cs = '1' and oe = '1' and we = '0') else (others=>'Z');

 -- Memory Read Block
  MEM_READ: process (address, cs, we, oe, mem) begin
    if (cs = '1' and we = '0' and oe = '1') then
      data_out <= mem(conv_integer(address));
    else
      data_out <= (others=>'0');
    end if;
  end process;

您可以使用条件为inout分配读取和写入数据.读取数据时,它由另一个模块驱动.写入时,它由内部驱动.

• 当由另一个模块驱动时(如在信号中),例如在所有'Z'和矢量"0101010"之间解析数据.数据将被驱动为"0101010".
• 在另一种情况下:另一个模块必须通过所有"Z"驱动数据,然后内部信号可以将其值赋予数据.

Answer 2

你需要一个明确的'Z'驱动程序.