如何:vhdl中的多维数组

Question

我正在尝试用VHDL创建一个5维数组,但我不确定如何设置和初始化这些位.

这是我到目前为止:

    type \1-line\ is array (4 - 1 downto 0) of unsigned (32 - 1 downto 0);
    type square is array (4 - 1 downto 0) of \1-line\;
    type cube is array (4 - 1 downto 0) of square;
    type hypercube is array (4 - 1 downto 0) of cube;
    type \5-cube\ is array (4 - 1 downto 0) of cube;

    signal mega_array : \5-cube\;
    begin
        process (clock, reset) begin
                if (reset == '1') then
                        mega_array <= '0';
                end if;
        end process;
    end behv;

Answer 1

一种方法是使用'(others =>'0')'.这是一种干净安全的方法,可以将向量的所有位设置为"0".您必须为阵列的每一层执行此操作.

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity test is
    port (
        clock : in std_logic;
        reset : in std_logic);
end entity test;

architecture behv of test is

    type \1-line\ is array (4 - 1 downto 0) of unsigned (32 - 1 downto 0);
    type square is array (4 - 1 downto 0) of \1-line\;
    type cube is array (4 - 1 downto 0) of square;
    type \5-cube\ is array (4 - 1 downto 0) of cube;

    signal mega_array : \5-cube\;

begin

    process (clock, reset)
    begin
        if (reset = '1') then           -- note: not '=='
            mega_array <= (others => (others => (others => (others => (others => '0')))));
        end if;
    end process;

end architecture behv;

请注意,虽然\1-...命名是正确的VHDL,但我不会用它来避免讨厌的工具问题.我不确定他们会来,但避免他们比解决他们更好.我会t_1line改用.