VHDL - 增加按钮事件的寄存器值

Question

我是VHDL的新手,我正试图弄清楚如何在Altera Cyclone II上做一些相当基本的事情.FPGA有四个按钮 - 其中两个需要编程以增加和减少所选寄存器(0-F),两者需要编程以增加和减少将在注册.这是我到目前为止:

entity raminfr is
    port (
        clk : in std_logic;
        we : in std_logic;
        a : in unsigned(3 downto 0);
        di : in unsigned(7 downto 0);
        do : out unsigned(7 downto 0)
    );
end raminfr;

architecture rtl of raminfr is
type ram_type is array (0 to 15) of unsigned(7 downto 0);
signal RAM : ram_type;
signal read_a : unsigned(3 downto 0);

begin

process (clk)
begin
    if rising_edge(clk) then
        if we = '1' then
            RAM(to_integer(a)) <= di;
        end if;
        read_a <= a;
    end if;
end process;

do <= RAM(to_integer(read_a));

end rtl;

有人可以提供一些关于如何编程按钮的基本示例代码吗？

Answer 1

您可以在时钟中进行简单的边沿检测process,然后只对上升沿做出反应.例如:

signal lastButtonState    : std_logic := '0';

process(clk)
begin
  if(rising_edge(clk)) then
    if(buttonState = '1' and lastButtonState = '0') then      --assuming active-high
      --Rising edge - do some work...
    end if;
    lastButtonState <= buttonState;
  end if;
end process;

为了使一切正常工作,您需要确保按钮以某种方式去抖动.许多开发板都有硬件RC电路,但你需要在你的代码中完成它(虽然这并不难 - 网上应该有很多例子).